It is already known that CMOSFETs (CMOS Field Effect Transistors) using CMOS (Complementary-Metal Oxide Semiconductor) technology are mainly used as the logic elements of current information processing systems such as computers. Further, it is known that finer design rules have been advanced for CMOSFETs with great effort in response to the need for higher performance of information processing systems. As already known, CMOS technology is based on planar technology, in which thin films of an insulator, a semiconductor, and a conductor are formed on a semiconductor substrate, the thin films are etched using photolithography or an impurity is implanted into the semiconductor substrate, and members and areas having been subjected to etching or impurity implantation are laminated to form predetermined devices. When an FET is constituted of a simple planar gate electrode using planar technology, a gate length affecting the performance of the FET is decided by the accuracy of patterning. The accuracy of patterning determines the limit of the finer design rules of FETs. Currently in order to exceed the limit of the finer design rules, studies have been conducted in view of sophistication of various process technologies including thin film formation, lithography, and etching or material development which is advantageous to the existing process technology.
However, the FETs with the planar gate electrode using CMOS technology are expected to reach a technical limit in about 2016. That is, various undesirable effects caused by a shorter gate length (and thinner oxide thickness) become more pronounced as MOSFETs advance in fine design rule. As a representative short channel effect, the following is known: an increase in off current and a reduced level of control due to hot electrons. A large off current increases power consumption. Considering that an operating frequency (clock frequency) tends to increase, an increase in power consumption per area is a serious problem.
Two approaches are available to exceed the technical limit. The first approach is to gradually extend the technical limit based on the current CMOS technology. The second approach is, for upcoming times of nanomolecular devices, to search for a logic device based on a new operating principle in the background of nanophysics aimed at physical phenomena of atoms and molecules.
Techniques classified into the first approach include attempts of material engineering, in which studies are conducted on a carbon nanotube used as the channel of an FET and a high-K dielectric film used instead of a gate oxide film. Further, a FinFET is studied which has a gate electrode (channel) shaped like a fin in the gate structure of a CMOSFET, and a multi(double)-gate FET is studied which has a plurality of (two) gate electrodes on a channel.
The second approach is to study principles and cannot make considerable progress overnight. It is necessary to make steady efforts and satisfactory results are not obtained at present. For example, non-patent document 1 describes the present circumstances of nanomolecular devices. In parallel with a new system such as QCA (Qauntum Celler Automaton), two-terminal devices having been studied in the past have received attention again as devices applicable to logic circuits, in the context of a new device technology of nanomolecular devices. For example, a configuration of method logic circuits is available which uses ordinary diodes. Non-patent document 2 describes a configuration method of logic circuits using Esaki diodes, which are NDR (negative differential resistance) devices. Further, non-patent document 3 describes a Y-branch switch which has been studied in association with the implementation of a BDD (Binary Decision Diagram).    [Non-patent document 1] R. Compano, L. Molenkamp, D. J. Paul, Technology Roadmap for nanoelectronics, European Commission IST Programme: Future and Emerging Technologies, Microelectronics Advanced Research Initiative, http://nanoworld.org/NanoLibrary/nanoroad.pdf    [Non-patent document 2] R. H. Mathews, J. P. Sage, T. C. L. Gerhard Sollner, S. D. Calawa, C.-L. Chen, L. J. Mahoney, P. A. Maki, and K. M. Molvar Proc. IEEE, vol. 87, no. 4, pp. 596-605, April 1999.    [Non-patent document 3] T. Palm and L. Thylen, “Designing logic functions using an electron waveguide Y-branch switch,” J. Appl. Phys. vol. 79, pp. 8076, May 1996.